The engineering decision
Measure the cell stack and equipment terminals during the same event. Then subdivide the difference until the dominant loss is located.
Have these inputs ready
- Synchronized load current and voltages
- Measurement points and return path
- SOC, temperature and event duration
- Controller and BMS event logs
Follow the voltage to the equipment
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Define the measurement boundaries
The open-circuit to loaded cell-stack change includes cell dynamics. The loaded stack-to-equipment difference is the loss across the intervening conductors and components. These quantities must be captured at the same current and time; comparing a rested voltage with a later BMS display can mix several different effects.
Measure both outgoing and return conductors. A ground-reference shift can reset electronics even when the battery remains above its nominal cutoff. Use appropriately rated differential or isolated instruments for the circuit; an earth-referenced oscilloscope ground can short a floating battery node.
Turn millivolts into a loss budget
At a hypothetical steady 100 A, a 0.30 V drop between the loaded stack and pack output implies 3 mΩ in that segment. Another 0.50 V between the output and equipment implies 5 mΩ in the cable and mating path. The external path dissipates about 80 W in total.
The stack itself falls from 52.0 V at a zero-current baseline before the step to 50.8 V at the selected sample time. Dividing this 1.2 V by the current step gives an apparent 12 mΩ pulse resistance. Record that sample time: polarization means a later sample can give a different result.
| Boundary | Drop | Apparent resistance | Power loss |
|---|---|---|---|
| Cell stack, before/after current step | 1.20 V | 12 mΩ at stated time | Dynamic cell estimate |
| Loaded stack → pack output | 0.30 V | 3 mΩ | 30 W |
| Pack output → equipment | 0.50 V | 5 mΩ | 50 W |
Choose the next branch from the evidence
| Observation | Next measurement | Likely investigation |
|---|---|---|
| All groups sag similarly | Repeat at controlled SOC and temperature | Cell capability, aging or excessive load |
| One group is an outlier | Group voltage plus independent verification | Mismatch, joint or sense connection |
| Stack stable; equipment voltage falls | Drop across each series segment | Fuse, switch, connector, cable |
| Reported sag without independent sag | Sense lead routing and sample timing | Measurement artifact |
| Voltage recovers after disconnect | Fault log captured before recovery | Protection trigger and load profile |
Keep the test reproducible
Use separate force and sense connections where possible. Place the sense points on the actual terminals of the segment being evaluated. Record current-probe offset, instrument range and sampling bandwidth. A slow logger can miss the minimum voltage of a short acceleration event.
Begin with a repeatable load step within the approved operating limits. Stop on an abnormal temperature rise, damaged connection or protection event. Repeat at the required service corners only after the first anomaly has been resolved.
Compare the repaired path with the original trace at the same SOC, temperature and load. A lower contact drop that simply moves the limiting condition into the cells is not a completed system validation.
Measurement & validation procedure
| Test / review | Record | Acceptance condition |
|---|---|---|
| Capture the event | Stack V, equipment V, current and timestamp | Traces share a time base and resolve the shortest event |
| Subdivide external losses | Millivolts across each segment and return | Sum agrees with stack-to-equipment difference within uncertainty |
| Verify corrective action | Before/after trace at matched conditions | Equipment voltage and temperature remain within limits |
Continue this engineering task
Related engineering guidance
Prepare the evidence for review
- Annotated measurement-point diagram
- Synchronized voltage/current capture
- SOC, temperatures and pulse duration
- Fault log before reset
Technical sources & claim support
References support the stated engineering principles. Worked examples use their explicitly stated assumptions.
- Keysight: How to Test Coin Cell Batteries ↗
Coin Cell Battery Testing and Modeling: four-wire sensing, pulse resistance, pulse width/rest time and defined cutoffs
Measurement principles illustrated with coin cells. Select the current profile, fixture, sampling, temperature and cutoff conditions for the actual cell or pack.
- Texas Instruments BQ76952 data sheet, SLUSE13B ↗
Sections 7 and 10–12: electrical characteristics, measurement, protection and FET control
Example of a monitor/protector architecture; capabilities depend on the selected IC and complete circuit.
- Molicel INR-21700-P45B product data sheet, revision 1.2 ↗
Cell specifications; discharge-rate and temperature characteristics
Cell-specific capacity, impedance and rate/temperature data; worked examples state their own input values.
Key claims and evidence
| Claim | Basis | Reference |
|---|---|---|
| Four-wire sensing reduces lead-resistance contribution | documentation | Keysight: How to Test Coin Cell Batteries |
| The external-path drop can be subdivided at synchronized current | inference | calculation |
| 0.8 V at 100 A corresponds to 80 W | calculation | calculation |