The engineering decision
Choose and report the DCIR sampling time from the application load, measurement bandwidth and intended physical interpretation.
Have these inputs ready
- Application peak duration
- Pulse current and voltage trace
- Tester rise time and sample rate
- Cell SOC and temperature
The sampling time changes the reported response
Scroll horizontally to view the full diagram →
One pulse produces several time-defined values
Resistance at time t is ΔV(t)/ΔI. At early time, fast conduction and instrument response dominate. At later time, polarization and transport contribute more strongly.
Illustrative values: a 50 A step with a 0.200 V drop at 100 ms gives 4.00 mΩ, while a 0.250 V drop at 1 s gives 5.00 mΩ. These invented values explain the arithmetic; actual results require measured synchronized samples.
References: A study of the influence of measurement timescale on internal resistance characterisation methodologies for lithium-ion cells; Comparison of Several Methods for Determining the Internal Resistance of Lithium Ion Cells
Long pulses move the battery state
A pulse transfers charge according to ΔQ = IΔt. As duration grows, the voltage difference can include movement along the OCV-SOC curve as well as the intended dynamic response.
Pulse heating can also change resistance during the measurement. Preserve current, voltage and temperature traces when the pulse is energetic enough for this to matter.
The shortest timestamp is not automatically best
Sampling too early can measure current-source rise time, fixture inductance, noise or channel misalignment. The timestamp must be late enough for the test system to resolve and early enough for the intended interpretation.
Use the actual duty cycle as the final acceptance test when its pulse sequence is known.
Measurement & validation procedure
| Test / review | Record | Acceptance condition |
|---|---|---|
| Resolve the test-system transition | Commanded and measured current plus synchronized voltage | Declared timestamp is outside unresolved rise-time or alignment error |
| Calculate resistance at stated times | R(t) values with SOC, temperature and pulse direction | Every reported value carries its timestamp and condition |
| Compare with the duty cycle | Predicted and measured minimum loaded voltage | Selected pulse time supports the application decision |
Continue this engineering task
Related engineering guidance
Prepare the evidence for review
- Application pulse definition
- Test-system bandwidth record
- Time-indexed resistance results
- Duty-cycle correlation
Technical sources & claim support
References support the stated engineering principles. Worked examples use their explicitly stated assumptions.
- A study of the influence of measurement timescale on internal resistance characterisation methodologies for lithium-ion cells ↗
Scientific Reports 8, 21 (2018); abstract and Figure 7: comparison at matched measurement timescales
Peer-reviewed cell study. Numerical values apply only to the tested cells, SOC, temperature and equipment.
- Comparison of Several Methods for Determining the Internal Resistance of Lithium Ion Cells ↗
Sections 4–5: DC step, AC resistance, impedance spectroscopy and pulse-duration effects
Peer-reviewed method comparison. The proposed timing and cell values are not universal acceptance requirements.
Key claims and evidence
| Claim | Basis | Reference |
|---|---|---|
| Calculated resistance increased with pulse duration for the tested cells and conditions | documentation | A study of the influence of measurement timescale on internal resistance characterisation methodologies for lithium-ion cells; Comparison of Several Methods for Determining the Internal Resistance of Lithium Ion Cells |
| Long high-current pulses can include voltage change from SOC movement | documentation | Comparison of Several Methods for Determining the Internal Resistance of Lithium Ion Cells |
| The application duty should determine the useful sampling window | workflow | engineering workflow |